Meta AR/VR Job | Display Electrical Engineering Manager
Job（岗位）: Display Electrical Engineering Manager
Type（岗位类型）: Engineering
Citys（岗位城市）: Sunnyvale, CA +1 locations
Date（发布日期）: 2024-11-5
Summary（岗位介绍）
Meta Reality Labs is the world leader in designing cutting-edge virtual and augmented reality systems. Join a team of expert engineers as we push the boundaries of technology to make the metaverse and wearable devices universal and pervasive. This is your opportunity to embark on the adventure of a lifetime as we turn science fiction into reality and shape the future.
The Display Panel Team, within the broader Display and Optics organization, is seeking a Display Electrical Engineering Manager to lead the development of Meta’s proprietary display silicon backplane and algorithm IP for wearable AR displays. As a key leader in the Display Panel team, you will collaborate closely with display micro-silicon architecture and pixel pipeline engineers, the Visual Quality team, and external silicon design vendors to design, evaluate, and integrate Meta’s proprietary visual quality IP into the display silicon backplane or SoC for future AR products. This role provides a unique opportunity to contribute to both forward-looking research and product-critical projects, requiring collaboration across multiple teams within Meta Reality Labs.
Qualifications（岗位要求）
Master's degree or above in Electrical Engineering, Computer Science, or a related field
10+ years of experience in the display industry, with a focus on electrical system, electron to photon conversion, optical systems and AR/VR/MR projection design
Proven technical expertise in display technologies, including OLED, LCD, LED, and LCoS
Experience leading cross-functional teams and collaborating with external partners
Effective communication and presentation skills
Experience to work independently and in a fast-paced environment
Interest for innovation and staying ahead of the curve in display technology
Description（岗位职责）
Manage a team including system architecture, display EE, pixel pipeline and image processing algorithm engineers
Define the end to end display panel architecture and incorporate the requirements meeting PRD across power, size, performance, and cost attributes
Drive image algorithm development and calibration strategy in partnership with other display pillar leads, including design for manufacturing to close loop on algorithms and product performance
Work across XFN partners to set up validation, verification, tuning, calibration, plans and other enabling support
Collaborate with silicon architecture and internal/external silicon design partners on driving execution backplane activities for wearable AR products including uLED, LCoS and emerging technologies
Prototype solutions using simulators, FPGAs, and non-form-factor modules to gather data and create an understanding surface predictive of final design performance
Work across organizations in defining the roadmap and long-term platform development strategy for display silicon, taking into account desired image processing approaches, light source and modulation technologies, outcoupling strategies, and combiner implementations
Additional Requirements（额外要求）
Ph.D. degree in Electrical Engineering
Experience in design and architect silicon backplane for microdisplay application
Familiar with Imaging Processing IP design
Good understanding of pixel pipeline for displays and silicon backplane architecture
Good understanding of the front-end analog/digital design flow: RTL design, logic synthesis, timing verification.
