Meta AR/VR Job | Signal Integrity and Power Integrity Engineer
Citys（岗位城市）: Sunnyvale, CA
As an Signal Integrity power Integrity Design Engineer on Meta’s AR Product Team, you will work directly with the AR design team to influence the design of Meta’’s AR prototypes and future line of consumer products. You will work on system level signal integrity and Power Integrity design and validation. Work scope includes SI/PI simulation, automation development, bring-up, validation and test in the lab for simulation correlation to improve EMC design quality for all design phases.
The individual filling this position is expected to perform independently on multiple projects, work within teams interfacing with other engineers and technicians, and collaborate well with different XFN team engineers and/or outside vendors to complete all necessary tasks.
We want people who can take an ambiguous requirement and can create highly constrained solutions into high-volume consumer products. The ideal candidate has a strong SI/PI design background, excellent simulation and lab measurement capability, experience in designing and manufacturing consumer technology products and a great team player can work with XFNs with great communication skills.
Bachelor’s degree in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience)
3+ years of experience in EM simulation and measurement areas
Solid EM fundamentals and familiar with EM simulation tools. Solid experience using Cadence Sigrity, PowerSI, OptimizePI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
Familiar with PCB and flex design and manufacture process
Experience delivering a product into manufacturing.
Perform Signal Integrity analysis, collaborating with different engineering teams to balance system/product constraints with MIPI CPHY, DPHY, MPHY, PCIE, USB and high speed clocks.
Perform pre-layout and post-layout simulation flow with a focus on PDN
Create simulation models and develop simulation methodology for SIPI design
Stackup review and layer assignment for High speed and PDN
Lead SIPI validation methodology and develop detailed engineering test plans
Validate PDN impedance in lab to correlate simulation results and improve design flow
Use simulation and lab data to support design troubleshooting and propose corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems
Analyze chip/package/PCB PDNs and make design trade-off and negotiate power budgets.
Provide design specifications and guidelines with clear risk tradeoffs to our XFN partners
Explore various design elements including different sensors, modules, memories, low/high speed buses, cables, components, flexible and rigid PCBs, their physics of operation, and impacts on system performance.
Provide system SI design guidance and perform post-layout review and optimization
Work closely with silicon team, EE design team and PCB layout team to optimize SI design based on the simulation data
Use simulation and lab data to support design troubleshooting and propose corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems.
Generate simulation report based on the data and communicate with XFNs with clear SI recommendation.
Master’s in electrical engineering, Physics, Mathematics, or related field (or equivalent experience)
5+ years of experience in EM simulation and measurement areas
Feel comfortable using different instruments such as network analyzer, oscilloscope, signal generator, scope and other related test equipment to measure the eye-diagram