Microsoft AR/VR Job | Principal SOC Logic Design Engineer
Job（岗位）: Principal SOC Logic Design Engineer
Type（岗位类型）: Engineering
Citys（岗位城市）: Raleigh, United States | Austin, United States
Date（发布日期）: 2021-10-29
Summary（岗位介绍）
Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, and performance modeling, and DevOps supporting the development of custom silicon. Microsoft's hardware teams are also expanding into new technologies such as quantum computing! We are looking for the best and brightest to join us in designing for the future!
Qualifications（岗位要求）
Basic qualifications:
BS/MS degree in Computer/Electrical Engineering with 8+ years of industry experience where:
- Demonstrated expertise with strong fundamentals in Computer Architecture, Digital Design, CPU/SoC design and verification principles as part of CPU, SoC and/or IP development.
- Experience withRTLdesignimplementation andmicro-architecture including either Clock& Reset, CPU, Cache, MMUs, DDR and/or interconnects
- Familiarity with design flows and methodologies in one or more of the areas: Lint, CDC, RDC, synthesis,timingand/or low powerdesign.
Preferred qualifications:
- Highly Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, Synthesis, STA)
- Strong understanding in clock crossing techniques with understanding in UPF (Low power intent).
- Experience in building and integrating any of the IPs such as Cores, PCIe, USB, Memory Controllers and DDR, Security engines to SOC
- Expertise in industry standard tools used for design abstraction,integrationand wiring.
- Expertise in front end design flows and methodologies: SCM, RTL partitioning, third party IP integration, LEC, bump map, CSR integration, memory map, and 1st order verification debug
- Expertise in clock/reset design and voltage/power domain design.
- Deep Domain knowledge in one or more of these areas:Clocking & PLLs, CPU, Fabric, memory controller, security engines, Caches, coherence, MMU, Industry standard interfaces/protocols, DDR
- Familiarity with high performance and low power design techniques.
- Strong understanding of SoC Design & Integration challenges at subsystem and full chip level.
- Good verbal and written communication skills.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
#MicrosoftRaleigh #MicrosoftAustin #OCP2021
Description（岗位职责）
The Silicon Engineering Computing Development team in Raleigh is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. Looking for highly motivated engineer to join our front-end RTL development team covering micro-architecture implementation, RTL Coding, IP integration and design quality assurance, for our projects We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an efficient manner.
In this high impact role on the team, you will be responsible for:
- Define the micro-architectural implementation spec for a functional block.
- Implement the micro-architectural specification in Verilog or System Verilog.
- Continue to grow your micro-architectural knowledge of your own blocks as well as other blocks in the SOC.
- Continue to assess and then refine the implementation for area, power and performance.
- Integration of various functional blocks into SOC.
- Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary.
- Perform design quality checks such as Lint, CDC, Low Power Intent
- Define, Implement, deploy new methodologies and train the team.
- Work with chip architects and design teams to understand architectural goalsandhigh-levelrequirements.
- Work with the physical design team to understand design requirements, create physical partitioning, and close constraints.
- Work with the verification team to ensure SOC quality.
- Delight your customers who receive your deliverable by providing high quality functional block on schedule and with professional integrity.
- Own the SOC implementation and integration strategy.
- Mentor and coach junior engineers
