Microsoft AR/VR Job | Senior DFT Verification Engineer

Job(岗位): Senior DFT Verification Engineer

Type(岗位类型): Hardware Engineering

Citys(岗位城市): Raleigh, United States | Sunnyvale, United States | Austin, United States

Date(发布日期): 2021-10-28


The silicon computing development team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.


  • 7+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP’s or systems.
  • Excellent debug skills for RTL and gate level simulations
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl.
  • Ability to work independently and in a team setting and be able to research innovative solutions for challenging business/technical problems
  • Solid technical aptitude and problem solving skills, take initiative, and must be result driven strong debugging skills
  • Strong plus if familiar with DFT methodologies such as Memory BIST and Scan
  • Good communication and analytical skills

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.



As a member of the DFT team, you will partner with Functional Design and Verification teams to develop test-based infrastructure, toolkits, and suites for the latest Microsoft designs. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. You will start from design and circuit specifications to develop environments, tools, and test plans to achieve coverage targets. Large scale, cross team collaboration will be expected as you participate in design and code reviews as well as provide your expertise to local and remote team members.

We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner.

In this high impact & highly visible role on the team, you will be have the following responsibilities:

  • Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects.
  • Work on infrastructure and test flow development for unit level and full chip verification.
  • Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion testing, and debug.
  • Help evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show ROI for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.