Meta AR/VR Job | ASIC Engineer, Emulation | Quest

Job(岗位): ASIC Engineer, Emulation | Quest

Type(岗位类型): Artificial Intelligence

Citys(岗位城市): Austin, TX

Date(发布日期): 2023-6-12


Meta is hiring ASIC Emulation Engineers within our Infrastructure organization. We are looking for individuals with experience in HW emulation and prototyping required to build System on Chip (SoC) and IP for data center applications.


B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering.

Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

3+ years of experience with EDA tools and scripting languages used to build tools and flows for complex emulation environments.

Experience with current emulation technologies and methods, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods.


Develop emulation testbenches in System Verilog and/or C/C++.

Deliver emulation and prototyping models from RTL on industry standard emulation and prototyping platforms.

Build and execute emulation test plan to ensure quality of the models and assist pre-silicon validation.

Drive emulation methodologies for HW verification and SW development.

Develop emulation tools, workflows and infrastructure in collaboration with RTL, verification, validation and SW teams for productivity during debug, runtime, and data analysis of results from emulation runs.

Bringup and debug PCIe, DDR and generic SOC interfaces.

Develop emulation validation components for validation efficiency in testing, debug and automation.

Develop and drive improvements using the latest emulation technology from industry.

Partner with vendors to debug issues and deploy new emulation capabilities.

Additional Requirements(额外要求)

Experience with verification, SoCs or similar designs.

Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of tradeoffs between performance and ease of debug.

Experience with SystemVerilog and C++ to model RTL components and transactors.

Experience with post-silicon bringup, debug and reproducing issues on emulator.

Experience with Palladium & Protium tools.

Experience with Python and Tcl scripting languages.