Meta AR/VR Job | Veterans Engineering Program – Design Verification Engineer | Oculus
Type（岗位类型）: Engineering | Hardware
Citys（岗位城市）: Sunnyvale, CA | Redmond, WA | Menlo Park, CA | Burlingame, CA | Seattle, WA
The Reality Labs (RL) team focuses on delivering Meta’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The RL silicon team is driving state of the art, breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware and algorithms.
We are excited to offer a new career development program to grow our RL Hardware team. We are seeking engineers, who are military veterans at all levels to work with a world-class group of researchers and engineers in Silicon/ASIC/VLSI, Machine Learning, Computer Vision, Computer Graphics, Security, Audio, Signal Processing, and more. You will support silicon team members in developing and implementing custom and semi-custom mixed signal ICs to drive our industry leading virtual and augmented reality systems. Military spouses may also apply.
This is a 12-month program with the Reality Labs silicon team. Once the program concludes, those who have demonstrated their abilities to succeed and make an impact at Meta will be considered for a full-time position.
Either BS Electrical Engineering/Computer Science or equivalent experience in a technical role in the military
Basic Coding and/or Scripting experience (Verilog, Python, C/C++, or similar)
Experience articulating complex engineering solutions to both technical and nontechnical cross-functional partners
Military Veteran, transitioning Service Member, or military spouse
Contribute to the development of efficient ASIC SoC Architecture through analog/digital design, design verification, physical design, test, methodology, compute infrastructure, or tooling
Work on our in-house IPs needed and how they need to be integrated, connected and verified
Learning and understanding of chip-level integration, verification plan development and verification
Learning and understanding and develop physical design implementation
Supporting the test program development, chip validation and chip life until production maturity
Work with emulation engineers to perform early prototyping
Assist with algorithm analysis, algorithm verification and improvement
Experience working in at least one of: Verilog/SystemVerilog, Python, C/C++ or similar
Understanding of digital ASICs design flows