Meta AR/VR Job | Facebook Reality Labs – Signal Integrity and Power Integrity Engineer

Job(岗位): Facebook Reality Labs – Signal Integrity and Power Integrity Engineer

Type(岗位类型): Engineering | Hardware

Citys(岗位城市): Sunnyvale, CA

Date(发布日期): 2022-3-30

Summary(岗位介绍)

Facebook Reality Labs is building products that make it easier for people to connect with the ones they love most. We are a team of world-class experts developing and shipping products at the intersection of hardware, software, content, and health. Our team has the responsibility for taking breakthrough concepts and delivering them to market at scale. We are seeking an SI/PI Engineer who has experience in SiP development, consumer electronics, and battery operated mobile products.

As a SIPI (Signal Integrity and Power Integrity) Engineer at Facebook, you will take a critical role in developing next generation Consumer Hardware Systems. You will be part of the EE design team, and responsible for building SIPI simulation process for boards/FPCs/SiPs, validating results in the lab for correlation to improve SIPI design quality. The person in this role is expected to work independently and lead projects, as well as work within teams interfacing with other engineers, technicians and/or outside vendors to complete all necessary SI/PI tasks. In particular, the role entails close collaboration with EE designers, system validation engineers, and vendors to help establish/validate system requirements and hardware specifications. We want people who work well in teams, can brainstorm big ideas, work in new technology areas, are able to drive a concept into a prototype, and can envision how a prototype could transition into a high-volume consumer product. Our ideal candidate has a strong SIPI design background, excellent simulation and lab measurement capability, and experience in designing and manufacturing space constrained consumer technology products.

Qualifications(岗位要求)

Bachelor’s degree in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience)

5+ years of experience in SIPI simulation and measurement areas

Experience in SIPI fundamentals, familiar with PCB and flex design and manufacture process

Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines

Hands-on experience using 2D/2.5D/3D simulation tools, creation of complex SIPI models, frequency and time domain simulation

Hands-on experience using high speed lab equipment and phy compliance test fixtures

Self-starter with analytical and organizational skills

Detail-oriented personality with solid documentation and reporting skills

Description(岗位职责)

Lead pre-layout and post-layout simulation flow with a focus on high speed interface and PDN, create simulation models and develop simulation methodology for SIPI design

Lead SIPI validation methodology and develop detailed engineering test plans

Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow

Use simulation and lab data to support design troubleshooting and propose corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems

Support multiple projects at the same time

Additional Requirements(额外要求)

Master’s or PhD in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience)

8+ years of experience in SIPI simulation and validation areas

Familiar with consumer hardware design, review and bringup process, CAD tools, constraint manager etc

Familiar with SI and PI co-simulation, system level 3D simulation and correlation to solve system design issues such as RF desense and thermal

Familiar with high speed interface protocol and SMPS regulator working mechanism

Familiar with HS simulations involving SiP substrate materials and mold caps, as well as correlating the performance before versus post molding

Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS

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