Meta AR/VR Job | DSP Architect (CV and Imaging) | Oculus
Job（岗位）: DSP Architect (CV and Imaging) | Oculus
Type（岗位类型）: Engineering | Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2022-2-17
Summary（岗位介绍）
Reality Labs (RL) focuses on connecting people through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of these products require custom silicon. The Silicon team is driving the state of the art forward with breakthroughs in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware, and algorithms.
We are seeking a DSP Architect who is excited about introducing groundbreaking capabilities in the fields of computer vision (CV), machine learning (ML), and imaging (ISP), through HW/SW partitioning and co-design of complex imaging and embedded algorithms into PPA optimized DSP + HW accelerators. They also subsequently engage in mapping and optimization of these workloads to the custom design programmable accelerators. The successful candidate will be required to contribute in defining architectural requirements by working with multidisciplinary teams and providing detailed design specifications of such compute platforms. They also code optimized kernels and libraries from high to low-level for current and future in-house heterogeneous compute and vision platforms, as well as architecting new methodologies that assist in analyzing, profiling and optimizing memory footprint, runtime performance, and power consumption of such workloads.
Qualifications（岗位要求）
Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
5+ years experience in CPU/DSP architecture, ISAs such as ARM, Tensilica, RISC-V, x86.
Experience with low-level SW optimization at instruction level, loop optimization, vectorization, data organization and caching. Programming SIMD, VLIW, and/or Vector processors.
Knowledge of ML, CNN accelerators and their architectural design trade-offs.
Description（岗位职责）
Study state-of-the-art algorithms in the field of CV, ML and Imaging, and subsequently architect appropriate SW-HW partitioning, for optimum trade-off in terms of power, performance and silicon area.
Influence algorithm and application optimizations in the context of low-power edge devices, including memory footprint vs compute trade-offs, accuracy KPI vs power/latency.
Develop accelerator specs, assist in micro-architectural specification, and collaborate with RTL and implementation teams.
Code CV, ML, imaging algorithms on customized processors, and accelerators in C and/or C++ for performance, latency, power, and memory. Perform low-level SW optimization at instruction level by loop optimization, vectorization, pipelining, data layout re-organization and cache/memory management.
Additional Requirements（额外要求）
MS or PhD in Electrical Engineering or Computer Science.
Familiarity with methods for partitioning a solution across hardware and software, and other multi-disciplinary boundaries in a system solution.
Theoretical knowledge in the field of computer vision, machine learning, and image processing, or ISP sensors.
Familiarity with ML frameworks like PyTorch/TensorFlow and model optimization toolkits.
Experience with domain specific languages and compilers such as halide, TVM and GLOW.
