Apple AR/VR Job | Strategic Silicon Engineer - Apple Mac
Job（岗位）: Strategic Silicon Engineer - Apple Mac
Citys（岗位城市）: Cupertino, California, United States
Date（发布日期）: 2025-2-24
Summary（岗位介绍）
Apple is seeking an enthusiastic strategic silicon development engineer for the Mac system design team. The candidate will help with silicon concept and feature development, system partitioning and silicon architecture, project management with Internal design and 3rd party vendors including troubleshooting of the silicons and their applications in the system. The Mac organization is looking for an outstanding engineer to support the system-level architecture, design, execution and validation aspects of Mac and Datacenter products development. The candidate will work within the Mac System organization and should have deep knowledge and familiarity with all aspects of mixed-signal silicon development, execution and failure analysis.
Qualifications（岗位要求）
B.S or M.S EE Degree with 10 years relevant work experience
Familiarity with all aspects of Mixed Signal Silicon development including proven experience in analog design processes, Digital design processes and silicon processes
Ability to manage complex silicon projects with internal and external silicon design teams including silicon fabs and IC test houses.
Lab testing expertise for evaluation boards and systems hosting mixed signal ICs.
Highly motivated, self-starter, able to work well with multi-functional teams in dynamic work environment.
Strong analytical skills and ability to guide critical investigations and decisions.
Description（岗位职责）
As a silicon engineer, you will work with Mac system architecture and design teams to define, architect and troubleshoot mixed signal ICs. The role involves coordination with cross-functional partners within Apple and outside of Apple during the development, execution and integration of the ICs in the Mac systems.
The candidate should be able to drive actions with internal and external silicon design teams proactively and independently ; those actions include but not limited to the following :
Author ERS that defines the IC and collect feedback from cross-functional teams.
Conduct detailed design reviews for ICs for all aspects of the design including Analog IPs, Digital IPs, silicon process, memory architecture, communication interfaces, etc.
Conduct reviews for methodologies and silicon executions processes that include digital and analog design flows, Clock Trees, IOs, DFT, DV, STA, CDC, etc.
Conduct reviews for PD (Physical Design), ESD, Packaging, ATE, Bench validation, Qualification, etc.
Additional Requirements（额外要求）
Ph. D EE with minimum 5 years experience.
Deep knowledge in DFT, DV, FA (Failure Analysis) techniques, memory interfaces, low speed and high speed communication interfaces and IC Packaging.
Proven experience with computer system level partitioning and silicon architecture.
Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.
Occasionally travel in the US and overseas to meet with internal design teams or 3rd party vendors.
