Meta AR/VR Job | Design Verification Engineer
Job（岗位）: Design Verification Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2024-2-26
Summary（岗位介绍）
We are growing our silicon design engineering team to support research silicon development for RL Research (RL-R) teams. We build small scale research silicon to demonstrate and integrate advanced IP into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP and fabrication techniques, to prove advanced architectures and to harden controls/algorithms for next generation AR/VR silicon solutions in support of our industry leading virtual and augmented reality systems.
As a Design Verification Engineer (DVEs), you will be a key contributor in planning, reviewing and executing our front-end verification efforts at the IP and sub-system levels. You will collaborate in improving DV methodologies and establishing best practices. Your expertise is needed in all phases of the chip development from DV planning to Gate Level Simulations and final sign off. Collaboration with other DVE is paramount for understanding the DV strategy and plan and executing on the same page and mindset. Our team is developing and implementing the next generation custom and semi-custom digital SOC’s/ASIC’s to drive our industry leading virtual and augmented reality systems.
Qualifications（岗位要求）
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
3+ years of experience as a Design Verification Engineer.
Proven communication and collaboration skills.
Knowledge of digital verification (SystemVerilog, UVM) and embedded firmware (C).
Proven debug experience.
Experience in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs.
Experience with vendor VIPs, integration and troubleshooting.
Description（岗位职责）
Self sufficient and detail oriented in all phases of Design Verification from IP to SoC level.
Provide feedback on IP/sub-system micro-architecture and RTL design.
Provide feedback on DV methodology, strategy and test planning.
Support earlier FW development with development bare metal drivers.
Help create and maintain design documentation including IP/SoC Verification Architecture document (collaborator/owner), IP/SoC Design Verification plan (collaborator) and SoC/chip bringup/validation plan (collaborator).
Contribute to DV efforts at block, subsystem and SoC level.
Additional Requirements（额外要求）
Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc.
Experience with Gate Level Sims (GLS).
Python (or similar) scripting experience.
Experience with embedded C FW/SW development for pre-silicon verification and post-silicon bringup.
Master’s degree in Electrical Engineer or Computer Engineer.
