Meta AR/VR Job | DFT Engineer
Job（岗位）: DFT Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2024-7-29
Summary（岗位介绍）
Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
As a DFT Engineer at Meta Reality Labs, you will play an integral role in implementing the DFT features and methods for our custom silicon developments. In this highly visible role, you will be an essential part of a cross-functional effort in getting functional products to millions of customers quickly.
Qualifications（岗位要求）
Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
4+ years of DFT experience
Knowledge of DFT methods - Scan, JTAG, iJTAG, MBIST, ATPG
Experience in implementing DFT features using industry standard DFT and design tools
Experience in simulating and debugging DFT patterns
Proficient in scripting and automation to enhance productivity
Description（岗位职责）
Work with the Silicon teams to document the DFT specifications and define the requirements
implement and verify DFT features to meet product requirements
Develop DFX (DFT/Design-For-Debug) methodologies based on industry standard tools
Work with designers on STA, physical, power and logical issues related to DFT
Work with test engineers to bring up test vectors on silicon
Work with lab bring-up teams to bring up test vectors in the lab environment
Additional Requirements（额外要求）
Experience of running SDF simulations, and debugging failures
Experience with STA constraints development and analysis for DFT modes
Experience with power-aware DFT
Experienced with developing and qualifying DFT STA constraints
