Microsoft AR/VR Job | Senior Design Engineer
Job（岗位）: Senior Design Engineer
Type（岗位类型）: Hardware Engineering
Citys（岗位城市）: Redmond, United States | Mountain View, United States
Date（发布日期）: 2022-1-14
Summary（岗位介绍）
Microsoft’s hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, and performance modeling, and DevOps supporting the development of custom silicon. Microsoft’s hardware teams are also expanding into new technologies such as quantum computing! We are looking for the best and brightest to join us in designing for the future!
We are seeking a motivated FPGA/ASIC Digital Design Engineer who is passionate about cutting edge hardware acceleration and would like to translate this passion into a commercial reality through a cloud service in Azure reaching thousands of customers and being implemented through millions of servers. Candidates should have FPGA and/or ASIC verification expertise to design IP for Microsoft’s next generation of cloud servers and applications. The candidate will contribute to a team developing IP for both FPGAs and ASICs. The successful candidate will be a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.
Qualifications（岗位要求）
Requirements:
- BS/MS in Electrical or Computer Engineering with 5+ years of experience
- Expertise in digital design including specification development, RTL design, synthesis and static timing signoff.
- Ability to write scripts using Perl, Tcl, Python, etc.
Preferred:
- Proven experience of successful IP designs for FPGAs or ASICs
- FPGA high-level synthesis design and compilation using HLS tools with C, C++ and OpenCL
- Knowledgeable in one or more industry standard interfaces such as AMBA AXI, PCIe, USB, and DDR/LPDDR is preferred
- Experience in FPGA design is desirable including an understanding the tradeoffs for mapping ASIC to FPGA or vice versa
- FPGA development environment tools expertise
- Experience with low power implementation methodologies
- Lab validation and power measurements / correlation
- Good communication skills, self-starter and ability to facilitate cross group collaboration across Microsoft internal groups and external vendors.
Microsoft Background Check:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
Description（岗位职责）
You will be responsible for all facets of digital design from reviewing architecture of features, microarchitecture of IP blocks, RTL design, synthesis, static timing analysis, validation, all the way to supporting the manufacturability of the part. Throughout the program you will be interacting with architects for feature definition, various design teams for leverage and collaboration, software, and system team for requirements.
