Microsoft AR/VR Job | Principal IP Silicon Logic Design Engineer

Job(岗位): Principal IP Silicon Logic Design Engineer

Type(岗位类型): Engineering

Citys(岗位城市): Raleigh, United States | Austin, United States

Date(发布日期): 2021-11-1


Microsoft’s hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more.Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling and DevOps supporting the development of custom silicon.


Basic qualifications

  • BS or MS degree in Electrical or Computer Engineering with 10+ years of industry experience.
  • Demonstrated expertise in Computer Architecture, Digital Design, IP and SOC development.
  • Highly proficient in Verilog/System Verilog.
  • Experience in delivery of ASIC IPs, sub-systems and/or top level SOC RTL for multiple projects.
  • Proven track record of silicon delivery as a team leader.
  • Experience in design flows and methodologies including Lint, CDC, RDC, synthesis,timing,and poweranalysis.
  • Strong understanding of IP development & SOC integration challenges at subsystem and full chip level.
  • Familiarity with clock/reset design and voltage/power domain design.
  • Familiarity with high performance and low power design techniques.
  • Strong verbal and written communication skills.

Preferred qualifications

  • Experience with front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power intent, linting, Synthesis, STA).
  • Experience in designing for testability, debug, and manufacturing.
  • Ability to write scripts using Python, Perl, Tcl, etc.
  • Expertise in industry standard tools used for design abstraction,integration,and wiring.
  • Expertise in front end design flows and methodologies: SCM, RTL partitioning, third party IP integration, synthesis, CSR integration, memory map, and 1st order verification debug.
  • Expertise in clock/reset design and voltage/power domain design.
  • Strong understanding in clock crossing techniques.
  • Strong understanding of UPF (Low power intent).
  • Domain knowledge in one or more of these areas is a plus:PCIe, Fabric, Security, CPU, Coherence, high speed interfaces/protocols.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#MicrosoftRaleigh #MicrosoftAustin #OCP2021


The Silicon Computing Development Team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are seeking highly motivated engineers to join our front-end RTL development team for RTL coding, IP Integration, and design quality assurance for our custom silicon solutions. We are responsible for delivering cutting-edge, custom CPU and SOC designs that can perform complex and high-performance functions in an extremely efficient manner.

In this role, you will:

  • Define the micro-architectural implementation spec for a functional block.
  • Implement the micro-architectural specification in Verilog or System Verilog.
  • Continue to assess and refine implementation for area, power, and performance.
  • Integrate various functional blocks into the SOC.
  • Exercise the functionality of the block by writing basic tests and debug for various features at IP and SOC levels as deemed necessary.
  • Perform design quality checks such as Lint, CDC, Low Power Intent.
  • Work with chip architects and design teams to understand architectural goalsandhigh-levelrequirements.
  • Work with the physical design team to understand design requirements, create physical partitioning, and close constraints.
  • Work with the verification team to ensure Design quality.
  • Own the SOC implementation and integration strategies.
  • Mentor and coach junior engineers.
  • Challenge the status quo with a growth mindset.