Meta AR/VR Job | Display Driver IC Pixel Pipeline Architect
Citys（岗位城市）: Sunnyvale, CA
Meta is the world leader in the design of virtual and augmented reality systems. Come work alongside expert engineers and research scientists to create the technology that makes VR pervasive and universal. Join the adventure of a lifetime as we make science fiction real and change the world.
The Display Architecture Team within the VR organization is seeking a Display Driver IC Architect to lead the implementation of Meta’s proprietary display IP for VR displays. As a member of the VR Display Team, the successful candidate will be working closely with other Display Driver IC (DDIC) architects, Visual Quality team, and DDIC vendors to design, evaluate performance, and embed Meta’s proprietary visual quality IP within the vendor’s DDIC for future VR products. This role offers involvement in a mix of forward-looking and product-critical projects, and requires close collaboration with multiple teams within the Meta Reality Labs.
The ideal candidate is familiar with common display algorithms such as sub-pixel rendering, foveation, Mura and burn-in compensation algorithms, is comfortable with programming languages such as Python or C++, and has extensive ASIC design background including RTL design, synthesis, and timing analysis. Deep understanding of the display pipeline is required.
Bachelors degree in Electrical Engineer or Computer Engineering or relevant industry experience
10+ years of experience in research, advanced optics development, or equivalent experience
5+ years of technical leadership experience working with multiple internal and external teams
Understanding of the front-end digital design flow: RTL design, logic synthesis, timing verification
Understanding of pixel pipeline for Displays and DDIC architecture
Effective communication skills and record of publications
Lead architecture and development of proprietary display IP for VR displays.
Collaborate with display algorithm experts to develop software (Python/C++) models of the algorithms.
Collaborate with visual quality teams to evaluate performance.
Collaborate with hardware prototyping teams to create hardware evaluation and platforms.
Collaborate with DDIC vendors to define high-level IP architecture consistent with vendors DDIC design.
Design and implement the algorithm in Verilog with optimized gate-count, meeting performance targets.
Create gate-level, timing-validated IP for transfer to DDIC vendors.
Collaborate with vendors to embed IP within the vendor’s DDIC.
Supervise chip-level verification.
Participate in DDIC design reviews with vendors and assess overall digital design flow including verification coverage, clock synthesis, timing signoff.
Collaborate with the system team to bring up and test the algorithm for production readiness.
15+ years of experience in research, advanced optics development, or equivalent experience
Ph.D. degree in Electrical Engineering or related field
Prior experience with architecture and design of display IP such as sub-pixel rendering, foveation, Mura, burn-in compensation algorithms
Familiar with compression IP design such as DSC