Meta AR/VR Job | ASIC Engineer, Design
Job（岗位）: ASIC Engineer, Design
Type（岗位类型）: Artificial Intelligence
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2023-5-28
Summary（岗位介绍）
Facebook is hiring ASIC Design Engineers within our Infrastructure organization. We are looking for talented individuals with deep RTL design experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.
Qualifications（岗位要求）
Currently has, or is in the process of obtaining a Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
Experience with Verilog or System Verilog.
3+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration.
Description（岗位职责）
Micro-architecture development.
RTL development using Verilog, System Verilog and HLS.
Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, selection and integration.
Collaboration with verification and emulation teams in test plan development and debug.
Collaboration with implementation team to close the design on timing and power.
Additional Requirements（额外要求）
Experience with Synthesis and Timing Closure.
Experience in data path development.
