Meta AR/VR Job | Analog Mixed Signal IC Integration Manager, Reality Labs
Citys（岗位城市）: Remote, US | Sunnyvale, CA | Redmond, WA | Austin, TX
Our silicon team is pushing the state-of-the-art with breakthrough work in computer vision, machine learning, mixed reality, graphics, power delivery, interconnect, displays, sensors, and new ways to map the human body. We work across the entire stack of system design, from transistors, architectures, firmware, and algorithms. Our chips will enable AR and VR devices to mix and match the real world with the virtual worlds throughout the day.
As a key technical lead in the analog mixed signal group at Meta, you will work with a world-class group of engineers creating high-performance and low-power custom designs for our AR/VR chips. Special focus areas will include breakthrough displays, sensors, interconnects and power. You will lead a small team of top digital design, AMS verification and firmware engineers, work with AMS designers and system engineers to define, develop and productize next generation custom AMS solutions that offer the best-in-class power efficiency, performance and form factor. We value excellent communication skills and strong cross-functional teamwork.
B.S. Electrical Engineering, Computer Science or equivalent experience.
10+ years of experience in Silicon design from specification to design flow and methodology.
2+ years of people management experience.
Expert digital designer.
In-depth knowledge in digital ASIC architecture and uArchitecture.
Experience being a self-motivated and team player.
Program management skills.
Lead a small team of digital design, AMS verification and firmware engineers.
Create high-performance and area/power efficient custom designs for Meta’s leading-edge AR chips.
Shape design and verification methodology and flows to improve execution quality and efficiency.
Work with external vendors as well as internal design teams for all phases of Si development.
Translate product concept and design requirements into uArchitecture documents and RTL design, while conducting power, area and performance tradeoffs.
Develop and review test plans, test benches and verification methodologies to validate analog circuit behavior along with digital components at chip level.
Third party IP evaluation and integration.
Collaborate with cross functional teams to develop post-Si validation plan and execute the validation plan.
Support device integration and system-level validation from IC perspective.
Ability to communicate clearly.
Ability to travel both domestically and internationally up to 20% of the time.
MS degree in EE or similar.
Solid experience in system Verilog UVM DV.
Knowledge in real-number behavioral modeling and AMS verification.