Meta AR/VR Job | Silicon Physical Design Engineer
Job（岗位）: Silicon Physical Design Engineer
Type（岗位类型）: Engineering | Hardware
Citys（岗位城市）: Remote, US | Sunnyvale, CA | Redmond, WA
Date（发布日期）: 2022-9-27
Summary（岗位介绍）
Reality Labs focuses on delivering Meta’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Meta Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
We are looking for a Silicon Physical Design Engineer who will work with a world-class group of researchers and engineers.
Qualifications（岗位要求）
8+ years of experience in Physical Design Engineering.
Bachelor’s degree in Electrical Engineering, or equivalent work experience.
Understanding of the RTL2GDS flow and design tape-outs in 10nm/7nm or below process technologies.
Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
Substantial experience working with EDA tools like DC, ICC2, Fusion Compiler, Primetime, Redhawk, Calibre.
Description（岗位职责）
Lead and own physical design implementation of large, multi-hierarchy, low-power designs including physical-aware logic synthesis, DFT (Design For Testability), floorplan, place and route, STA (Static Timing Analysis), IR Drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Deliver physical design of an end-to-end IP and integration into an ASIC/SoC design.
Additional Requirements（额外要求）
Experience in running physical-aware logic synthesis, achieving optimal synthesis QoR and converging block QoR to tape-out quality on low power designs.
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in Block-level and hierarchical floor-planning, power grid planning.
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
Experience with TCL and Python programming.
