Meta AR/VR Job | Silicon Engineering Manager, Reality Labs

Job(岗位): Silicon Engineering Manager, Reality Labs

Type(岗位类型): Hardware

Citys(岗位城市): Remote, US | Sunnyvale, CA | Redmond, WA | Seattle, WA

Date(发布日期): 2022-5-13


You will be heading to manage a talented team of silicon engineers working on DSP and Machine Learning, enabling new audio signal processing technologies. The role requires you to be an expert in accelerator design with strong implementation, low power, methodology, and silicon architecture background. You will lead the team to closely collaborate with the architecture, reference design teams, firmware and software application team to build IP(s) used in AR/VR products. You must have experience running teams working in an agile environment.


MS in EE/CS or equivalent.

10+ years of experience in architecture, microarchitecture, IP lead, execution, or implementation of IP, DSP, or ML accelerators.

Track record of successfully delivering SoC’s or accelerator IP’s into mass production.

Track record of leadership (growing, supporting, and mentoring a healthy team). Demonstrated experience scaling up your team. Working across large organizations.


Lead team working on DSP and Machine Learning for vertical audio IPs starting from architecture, from design to physical design and system validation.

Recruit top talent and develop key relationships with design service providers.

Work with cross-functional leads, including silicon architects, SOC teams, software, systems architects, product managers, and researchers, to develop a steady stream of industry leading accelerators aimed at the most impactful use cases.

Develop a strategy for delivering IPs across several chips targeted to low power wearable devices.

Recruit top talent and develop key relationships with design service providers.

Additional Requirements(额外要求)

Experience in SoC integration and ASIC architecture.

Experience in SoC µarchitecture.

Experience in RTL coding and synthesis in SystemVerilog, Verilog, or VHDL.

Experience in Design Verification OVM/UVM/System Verilog.

Experience in DSP or Machine learning, AI, Artificial Intelligence accelerators.

Experience in PD of IP integration.

Experience in C/C++ programming for DSP Accelerator APIs.

Experience in DFT/Testability requirement and test program definition.

Experience in Python (or similar) scripting experience.

Experience in Agile process improvements and methodology.

Experience working with vendor partners.

Interest in tackling diverse challenges and must demonstrate good interpersonal skills.