Meta AR/VR Job | Silicon Performance Architect
Job（岗位）: Silicon Performance Architect
Citys（岗位城市）: Remote, US | Sunnyvale, CA | Redmond, WA | Austin, TX
Reality Labs focuses on delivering Meta’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Meta Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
We are looking for a Silicon Performance Architect who will work with a world-class group of researchers and engineers. This ideal candidate will understand the full spectrum of silicon performance, analysis, and projections from algorithms on generic compute units to custom silicon IP blocks, traditional compute benchmarking, and SOC and System level implications.
8+ years of experience with production silicon.
2+ years of experience with developing architecture simulators.
2+ years of experience with methods for partitioning a solution across hardware and software, digital, and other multi-disciplinary boundaries in a system solution.
2+ years of experience evaluating architectural trade-offs of performance, power, and area.
Experience employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary system issues.
MS EE/CS or equivalent experience.
Develop detailed performance models, analyze performance and optimize silicon architecture for high performance at lowest power for AR/VR use cases which includes functions such as image processing, computer vision and perception, machine learning, and CPU/GPU benchmarking.
Perform detailed SoC level performance characterization of interconnect and memory data paths, carry-out throughput and QoS analysis, and explore novel memory architectures to achieve best perf/mW.
Surpass state-of-the-art for metrics such as compute, bandwidth and power consumption.
Work across disciplines, brainstorm big ideas, build new methodologies, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product.
Understand the tradeoffs between general purpose and custom compute mechanisms, be able to model data-flows, and create detailed cost/benefit analysis.
Work with other Architects in undertaking performance analysis, modeling, and projections. Produce detailed documents and SystemC models matching the proposed ASIC implementation, and perform detailed tradeoff analyses for executive review and product roadmap decisions.
Work with DV teams to drive pre and post-silicon performance validation by creating power and performance test plans, develop tests and own RTL debug to root-cause bottlenecks and miscorrelations.
Experience in top down high-level-model to HW mapping.
Experience in SystemC/TLM2 performance modeling.
Experience with cycle-accurate full-system SoC performance model environments.
Experience with state-of-the-art pre-silicon power estimation methodologies.
Experience in custom IP block performance estimates.
Experience programming in C/C++.
Experience with RTL simulation and performance analysis.
Experience working effectively as an individual and in a multidisciplinary team.
Capable of dealing with ambiguity with a fast changing consumer electronics field.
Results oriented, self-motivated, proactive with demonstrated creative & critical thinking.
Experience collaborating and/or leading in a team environment.
Experience with post-Silicon performance test development and characterization.