Meta AR/VR Job | Si Package Design Engineer

Job(岗位): Si Package Design Engineer

Type(岗位类型): Design | Engineering, Hardware

Citys(岗位城市): Taipei, Taiwan

Date(发布日期): 2022-3-15

Summary(岗位介绍)

We are building a competency in packaging design and technology to support the development of custom Silicon for AR/VR hardware as well as to develop packaging solutions that are optimal for our device ID and system level performance.

Qualifications(岗位要求)

Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Bachelor’s degree in electrical engineering or equivalent experience

5+ years’ experience in designing packages or modules for mobile or computing products

Experience working with advanced packaging tools such as Mentor Xpedition, Cadence APD, and SIP

Description(岗位职责)

Perform package design for advanced custom Si comprising single-chip/multi-chip and SiP/module packaging. This includes: design feasibility studies and analyses, package design/layouts based on Si chip IO, electrical performance and system ID/form factor requirements

Participate in Si/package/PCB/system co-design work collaborating with downstream system design teams and upstream Si designers to develop holistically optimal solutions

Co-work with internal Si, architecture and system teams and externally engaged partners, design houses and OSAT companies

Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products

Additional Requirements(额外要求)

Masters degree in electrical engineering or equivalent experience

Familiarity with advanced packaging technologies like Fan-out wafer level, Flip Chip etc.

Familiarity with SI-PI analysis and tools

Experience working with MCAD tools such as SolidWorks, AutoCAD and interconversion of package design databases to MCAD files

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