Meta AR/VR Job | Digital Design Research Scientist

Job(岗位): Digital Design Research Scientist

Type(岗位类型): Engineering | Hardware, Research

Citys(岗位城市): Sunnyvale, CA | Redmond, WA

Date(发布日期): 2022-3-8


We are looking for a Digital IC Designer to create innovative designs at the forefront of custom sensor technology, to enable breakthrough new depth sensing architectures delivering the best-in-class performance in small form factors and ultra-low power systems. The ideal candidate is enthusiastic about exploring and tackling new on-sensor compute architectures and sometimes ambiguous technical challenges, is engaged in deep collaboration across internal and external teams of passionate technologists that result in detailed depth sensor analyses, critical tradeoff evaluations, and sensor architectural execution strategies.

The scope of this role in the depth system architecture team will be a technical lead in creating, specifying, and reviewing new approaches to achieve high-end depth system performance in very constrained area and power efficiency requirements in the AR and VR space.


Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Ph.D. in Electrical Engineering/Computer Science or equivalent experience.

3+ years of experience as a Digital Design Engineer.

Experience in RTL coding, synthesis and/or SoC Integration.

Experience with at least 1 procedural programming language (C, C++, Python, etc.).

Experience communicating clearly and working effectively in a collaborative team.


Explore, propose, and create innovation high-performance digital control architecture proposals within stringent area and power efficiency constraints, targeting Meta’s leading-edge AR and VR devices.

Draft and own detailed specification documentation for internal and external partners.

Participate in and drive deep technical weekly reviews with key external design partners, from top level architecture, critical blocks, functional models, and RTL.

Contribute to scalable architecture designs for low-power Computer Vision and ISP IP designs.

Drive the top-level architecture definition and develop the necessary RTL.

Drive the chip-level integration, verification plan development and verification.

Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.

Contribute to ASIC digital architecture, design and verification.

Support the test program development, chip validation and chip life until production maturity.

Work with FPGA engineers to perform early prototyping.

Support hand-off and integration of blocks into larger SOC environments.

Assist with performance/power analysis of IP models.

Run simulations to predict system performance and power, and validate functionality.

Close collaboration with chip and block architects to understand macro floorplan, power distribution, and signal interfaces.

Develop scripts as necessary to improve productivity and reliability.

Participate in process improvements and complete any assigned circuit design task with minimal supervision.

Travel both domestically and internationally up to 10% of the time.

Additional Requirements(额外要求)

Familiar with CMOS image processing, depth performance analysis, imaging algorithms.

Experience with HLS flow for data path implementation.

SystemVerilog OVM/UVM experience.

Experience in SoC integration and ASIC architecture.

Experience with low power design and optimization.

Experience with design synthesis and timing optimization.

Experience transferring technology from research into a shipping product.