Meta AR/VR Job | Display Panel Design/Process Engineer

Job(岗位): Display Panel Design/Process Engineer

Type(岗位类型): Hardware

Citys(岗位城市): Sunnyvale, CA | Redmond, WA

Date(发布日期): 2022-2-17


The Reality Labs (RL) Platform Display and Optics (D&O) team focuses on moving the state-of-art display and optics technologies forward for Meta products, which gives people the power to build community and bring the world closer together. The team is responsible for the technology development and maturation, component design, manufacturing process advancement, and test & integration of display and optics module for all RL products.

As a Display Panel Design and Process engineer, you will be a member of our Display and Optics organization, taking a lead in display panel architecture to set the technical goals, lead the development of leading-edge technologies and designs, and work with the current and evolving ecosystem to provide differentiating capabilities to our HW platforms. You will be part of a group of highly talented engineers at the forefront of the innovation for AR/VR and portal products.


3+ years of experience in the display and/or Silicon industry

Experience in panel architecture scoping and definition with various display technologies

Experience in characterizing panel optical and electrical performance

Experience in developing, designing and manufacturing high volume consumer product

Experience communicating with cross-functional partners and external vendors

Project management, communication skills and people skills


Lead engineering activities on advanced display design for new display applications

Work closely with cross functional teams and external display partners to develop the future display technologies and bring up design for new panel products

Resolve design and flow issues related with circuit and pixel design, identify potential solutions and drive execution

Work closely with display IC, panel and module vendors throughout the design, sample, and engineering validation phases to address any design, production, and quality issues

Partner with internal and external teams to develop uOLED displays based on silicon chips with specific process lines

Design and optimize uOLED circuit and layout within small pixel/cell pitch

Develop uOLED display silicon process and transfer existing silicon technologies into and out of various process lines

Process control monitor (PCM) statistical analysis to optimize device structure and process module

Design rule validation and optimization for uOLED display specifically silicon processes and devices

Support failure analysis to improve defect rate, yield and process quality

Willingness and ability for 30% International travel to Asia

Additional Requirements(额外要求)

M.S degree in Electrical Engineering, Material Science or Engineering, Physics or related

Hands-on skill on Pixel and panel design, layout, parasitic parameter extraction and panel modeling

Experience performing computer modeling and simulation with SPICE

Experience in display pixel, gate driver designs is preferred

Experience in characterizing panel optical and electrical performance is preferred

Hands-on experience with transistor level design and verification of key analog blocks, including ADC/DAC, PLL, LDO, temperature sensor, OPAMP

Experience with Cadence design environment and mixed-mode verification

Experience in CIS and low-noise analog design

Experience with high voltage or mixed-voltage analog IC design

Experience with block level and chip level analog layout

Expertise on analog layout platforms such as Cadence or Mentor and full set of layout verification tools including LVD/DRC checking tools

Knowledge of RC delay, IR drop, coupling capacitance, electromigration, ESD and latch up

Experience with design and evaluation of physical and electrical design rule test structures

Skills for computer tools: experience with layout edit software, experience with statistical data processing software, experience with device and process TCAD simulation tools

Knowledge of one or more of the following technologies: Bipolar, CMOS, Depletion MOS, CMOS Image Sensor (CIS), Non-Volatile Memory (NVM), High voltage CMOS

Back-end processing experience such as wafer dicing, wire bonding, etc.