Meta AR/VR Job | Mask & Layout Process Engineer
Job（岗位）: Mask & Layout Process Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Cork, Ireland
Date（发布日期）: 2022-2-4
Summary（岗位介绍）
At Meta, we are developing the future of AR/VR displays. As a Mask/Layout Engineer within Reality Labs, you’ll be a critical member of a multi-disciplinary team contributing to our efforts to production, research, develop, and evaluate new architectures. Your on-hands role will focus on drawing layouts, implementing correct alignment marks, ordering and documenting masks as well as a high degree of communication around DRC, VMS, DRM. You will work closely with internal Meta Reality Labs teams, academic institutions, external partners, and vendors to ensure a reliable end-to-end verification process for our RGB LED-based light source architectures. Ideal team members are adaptable and resilient, eager to approach unfamiliar problems with curiosity and tenacity, and flexible to travel and take on possible assignments at partner locations.
Qualifications（岗位要求）
Degree in Electrical Engineering, Physics, Chemistry, Materials Science or Nano materials or related subject
5+ years of experience with the design-to-mask workflow (schematic, simulation, layout, physical verification, GDSII, mask)
5+ years of experience working with commercially available EDA tools for reticle build, such as those available through Cadence, Synopsys, or Mentor Graphics
Experience in custom DRC and LVS definition and/or coding
Knowledge of layout effects and best layout practices
Basic knowledge of semiconductor process integration
Description（岗位职责）
Creating, Defining and Sustaining the overall mask and layout business process internally and covering XFN partners as well as external partner facilities
Responsible for the mask request system, including assignment of priorities while considering different needs
Owning the mask business process (DRM) for using, ordering, storing layouts and mask
Drive, define and verify DRC’s, VMS, … and implement them actively in new requests together with the process and integration engineers while having all locked in Cadence
Support verification and general layout/mask work with our external partner
End to End owner (backplane – uLED – packaging) for our POR Architecture’s ensuring all safety measures are in place, ensuring mask requests and changes are running through verification, ensuring different areas are heard (CMOS backplane requirements, uLED requirements, process requirements, and package requirements)
Additional Requirements（额外要求）
Layout experience in different sectors for the semiconductor industry (e.g. one or more of CMOS, LED, Memory, Power)
On-hands experience in Lithography manufacturing processes
Keen interest in improving layout methodology
Interpersonal and communication skills
Capable of accepting responsibility and showing initiative/innovation in the layout and development of our product
