Meta AR/VR Job | Digital Design Engineer
Job（岗位）: Digital Design Engineer
Type（岗位类型）: Research
Citys（岗位城市）: Sunnyvale, CA | Redmond, WA | Austin, TX
Date（发布日期）: 2022-1-7
Summary（岗位介绍）
We are growing our digital design engineering team within Facebook Reality Labs Research (FRL-R) Graphics. You will use your digital design skills to implement and optimize state of the art graphics algorithms and systems. You will collaborate with silicon architects in developing and implementing next generation custom ICs to drive our industry leading virtual and augmented reality systems.
We are developing the next generation of graphics solutions for AR/VR. You will own connecting our graphics algorithms together and demonstrating end-to-end operation of our designs. You will drive integration of our IPs into ASIC systems. You will also contribute to prototypes of these systems to enable rapid iteration on our designs. If you’re the sort of person who is excited by the opportunity to redefine how design and verification of large scale digital systems is performed, we’d be excited to talk to you.
Qualifications（岗位要求）
BS Electrical Engineering or Computer Engineering
6+ years of experience as a digital design engineer and/or a microarchitecture lead
Experience in RTL coding and synthesis (SystemVerilog or VHDL)
Experience in microarchitecture development
Experience with on-chip bus protocols (AXI, AXI-Lite, AHB, etc.)
Experience as a digital designer at both the block and the SoC top-level
Experience with EDA tools (simulator/debug/synthesis/timing analysis) from major vendors (Synopsys/Cadence/Mentor)
Description（岗位职责）
Develop efficient IP microarchitectures and designs
Perform system-model-to-RTL translation
Perform hand-off and integration of IP blocks into larger SoC environments
Make area, power and performance tradeoffs in defining next generation IP’s and SOC’s
Develop RTL for graphics algorithms and graphics IP cluster
Work with early prototypes
Assist with algorithm analysis, verification and improvement
Perform third party IP assessment for integration into SoC’s
Support IP/SoC/bringup/test/validation and chip life until production maturity
Additional Requirements（额外要求）
Master’s degree in EE or CE
Experience developing design environments/methodologies from scratch
Python3 scripting experience
Experience leading small teams of digital designers
Experience in SoC integration and ASIC architecture
Experience implementing and validating high speed interfaces like PCIe, USB, MIPI
SystemVerilog OVM/UVM experience
Experience with SoCs and GPUs
Experience with design using NoC topology
Experience in DFT/Testability requirement and test program definition
