Meta AR/VR Job | Silicon Physical Design Engineer Intern, Digital Design & Implementation

Job(岗位): Silicon Physical Design Engineer Intern, Digital Design & Implementation

Type(岗位类型): Design | Research

Citys(岗位城市): Sunnyvale, CA

Date(发布日期): 2021-12-15


Reality Labs (formerly Facebook Reality Labs) focuses on delivering Meta’s vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware and algorithms.

We are seeking an intern to explore semi-custom design implementation and exploration around memory implementation structure and quantify PPA benefits on the design. In this role, you’ll partner with the architects, designers, methodology and flow team to implement semi custom designs in high efficiency hardware accelerators.

Our internships are twelve (12) to sixteen (16) weeks long and we have various start dates throughout the year.


Currently has, or is in the process of obtaining, a Master’s degree in electrical engineering or a related field

Background in Digital Design and VLSI

Understanding of memory hierarchy, implementation option and trade-offs

Understanding of Synthesis, static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis is required

Scripting and programming experience using TCL, Python, Skill and Make

Interpersonal experience: cross-group and cross-culture collaboration

Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment


End to end performance and power optimization of custom compute unit

Explore various microarchitecture and implementation ideas through semi custom or ASIC design and analyze Power, Performance and Area trade-offs

Build semi custom digital circuit/design and verify functional and timing correctness using industry proven ASIC methodology

Explore various memory implementation options like register file, latch array , SRAM and perform PPA trade-off analysis

Additional Requirements(额外要求)

Currently has, or is in the process of obtaining, a PhD in electrical engineering or a related field

Knowledge of EDA tools like Design Compiler/Genus, PrimeTime, Redhawk-SC, HSPICE is a plus

Intent to return to degree-program after the completion of the internship