Meta AR/VR Job | Silicon Performance Engineer Intern, Custom Silicon
Type（岗位类型）: Design | Engineering, Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: Before 2021-12-14
Reality Labs (RL) focuses on delivering Meta’s vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Silicon team at Meta is driving the state of the art forward with breakthrough work in Computer Vision, Machine Learning, Mixed Reality, Graphics, Displays, Sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware and algorithms.
We are seeking exceptional interns with a background in Performance Modeling, Simulation Methodologies, Computer Architecture, and HW/SW Co-design to join our SoC Performance team. This team focuses on modeling and power/performance optimization of custom Silicon that enables compelling end user experiences on mobile AR/VR systems. In this role, you will partner with Architects and Chip designers to build high accuracy performance models that mimic the SoC architecture and project performance for key AR/VR use cases. We expect that you have experience in building performance models and exposure to heterogeneous hardware architectures.
Our internships are twelve (12) to sixteen (16) weeks long and we have various start dates throughout the year.
Currently has, or is in the process of obtaining, a Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.
Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment.
Experience in computer architecture through undergrad/grad course work.
Experience in software design abilities with experience in C++.
Experience in performance modeling and architectural exploration methodologies.
Experience in hardware power, performance and area trade offs.
Carry out performance & power architecture exploration through detailed modeling and analysis of one or more of the following functions/components: custom compute components, shared interconnect in a heterogeneous SoC, shared cache/memory subsystem in a heterogeneous SoC, and/or traditional DRAM controllers and 3D stacked memory.
Create simulation infrastructure that will enable agile development of performance models for custom hardware.
Understand use case data flows, access patterns and working set sizes of various subsystems in the SoC.
QoS, latency and throughput analysis for heterogeneous platforms consisting of multiple agents with competing resource requirements.
Currently has, or is in the process of obtaining, a Master’s or PhD degree in Computer Science, Electrical Engineering or related field.
Intent to return to degree-program after the completion of the internship/co-op.
Experience in HDL to SystemC compilers such as verilator.
Experience in the analysis and exploration of heterogeneous multi-agent platforms.
Research or industry experience in computer architecture and performance modeling.
Publication track record (e.g., ISCA, ASPLOS, MICRO, HPCA, DAC, NOCS, ISPASS, PACT, etc.) in high performance architectures, 3D stacked memory, PIM, or heterogeneous memory systems.