Meta AR/VR Job | Engineering Intern, Design for Test
Job（岗位）: Engineering Intern, Design for Test
Type（岗位类型）: Artificial Intelligence | Engineering, Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: Before 2021-12-14
Summary（岗位介绍）
Reality Labs (RL) focuses on delivering Meta’s vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. The Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
Our internships are twelve (12) to sixteen (16) weeks long and we have various start dates throughout the year.
Qualifications（岗位要求）
Currently has, or is in the process of obtaining, a Bachelors or Masters degree in Electrical and Computer Engineering, or related field
Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
Knowledge of digital design fundamentals and computer architecture
Experience with Python, Perl, TCL or equivalent shell scripting language
Familiarity with SoC/ASIC design flow
Description（岗位职责）
Develop and automate Design for Test (DFT) flows
Perform DFT rule checks using commercial DFT tools and work with designers to resolve issues
Develop simulation testbenches to verify DFT implementation
Review IP specifications to establish required DFT features
Additional Requirements（额外要求）
Intent to return to degree-program after the completion of the internship/co-op
Currently has, or is in the process of obtaining, a PhD degree in Electrical and Computer Engineering, or related field
Knowledge of SOC design flow and DFT practices is a plus, e.g., At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG)
Experience writing Verilog RTL and developing simulation testbenches
Experience with commercial EDA tools for synthesis, simulation, DFT and ATPG
Knowledge of industry test standards (IEEE1149.1, IEEE1500)
Interpersonal experience: cross-group and cross-culture collaboration
