Meta AR/VR Job | Research Engineer, Silicon (PhD)
Job（岗位）: Research Engineer, Silicon (PhD)
Type（岗位类型）: Hardware
Citys（岗位城市）: Redmond, WA
Date（发布日期）: Before 2021-12-14
Summary（岗位介绍）
Facebook Reality Labs Research (FRL Research) brings together a world-class R&D team of researchers, developers, and engineers with the shared goal of developing AR and VR across the spectrum. The Surreal group at FRL Research is seeking exceptional research engineers to solve the next generation of research challenges on the path to building future machine perception enabled technologies. As a Silicon Research Engineer, your role is to collaborate with other researchers and engineers of the team in building FPGA prototypes and custom silicon chips that serve as a proof of concept for future AR and VR technologies. This involves contributing to all steps of custom silicon development, including but not limited to, software-hardware (SW-HW) co-design, architecture and microarchitecture design, physical design, verification, prototyping, and power/performance estimation.
Qualifications（岗位要求）
Currently has, or is in the process of obtaining, a PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Experience with Hardware accelerator design and architecture.
Experience with SW-HW co-design of computer vision and machine learning algorithms.
Experience in RTL coding.
Experience in digital design and verification.
Experience working on multidisciplinary projects.
Interpersonal experience: cross-group and cross-culture collaboration.
Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
Description（岗位职责）
Research, develop and prototype advanced tightly integrated hardware and software technologies in the domain of computer vision and machine learning.
Work with FPGA engineers to perform early prototyping.
Contribute to the process of designing a prototype throughout its lifetime.
Support integration of blocks into larger SoC environments.
Define efficient ASIC design flows/methodologies.
Collaborate with team members throughout the lifetime of a project, from prototyping to technology transfer and deployed products.
Additional Requirements（额外要求）
Experience with FPGA and/or ASIC.
Experience with High-Level Synthesis (HLS).
Experience with synthesis and SoC Integration of IPs.
Python or similar scripting experience.
Experience with high speed interfaces like PCIe, USB, MIPI.
Experience with silicon vendor management.
Broad understanding of the full machine vision pipeline from sensors to high-level algorithms.
Proven track record of achieving significant results as demonstrated by grants, fellowships, patents, as well as first-authored publications at leading workshops or conferences such as DAC, DATE, ISSCC, VLSI, ISCAS, ISCA, MICRO ASPLOS, etc.
