Apple AR/VR Job | DRAM Design Validation Engineer
Job（岗位）: DRAM Design Validation Engineer
Citys（岗位城市）: Cupertino, California, United States
Date（发布日期）: 2024-12-12
Summary（岗位介绍）
Do you love crafting elegant solutions to highly sophisticated challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!
As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM memories with SoC devices.
Qualifications（岗位要求）
PhD or MS or BS Degree with 5+ years in DRAM development.
Description（岗位职责）
Work with our design, verification and integration engineers to ensure memory controller and PHY requirements are well defined and cover the scope of DRAM based corner cases.
Collaborate with Architecture, MCU, DDRPHY and DRAM vendors for Apple’s main memory feature.
Ensure DRAM simulation meets Apple's requirements.
Ensure the internal and external DRAM silicon and package level testing needs are met.
Debug RMA material with apparent DRAM related defects.
Collaborate with the DRAM vendors to improve the DRAM performance and power on Apple systems.
Drive the roadmaps and specs of memory vendors for next technology node devices.
Additional Requirements（额外要求）
Expert in DRAM cell architectures
Expert of DRAM memory organization and periphery design for low DRAM power
Expertise in DRAM simulation
Experience in memory interface verification with understanding DDR-PHY and Memory Controller
Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5) characterization and qualification
Understanding of memory test patterns
Knowledge of DRAM reliability
Knowledge with innovative packaging technology (POP, TSV, etc.) and their relationship to DRAM signal/power integrity
Previous experience in Failure Analysis of DRAM devices
Excellent hardware and software debug skill
Experience working with the major DRAM vendors
Strong background in computer architecture
Programming experience in C/C++
Excellent interpersonal skills and teamwork
