Meta AR/VR Job | Performance Modeling Engineer
Job（岗位）: Performance Modeling Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2024-11-14
Summary（岗位介绍）
We are currently seeking a machine learning performance modeling engineer to support the development of a custom machine learning software/hardware verticals and use cases optimized for AR/VR systems. As part of the machine learning performance modeling team, you will help build performance modeling and analysis toolchains for machine learning workloads. You will work in close collaboration with the groups developing the hardware, system software and SoCs for AR/VR devices.
Qualifications（岗位要求）
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Experience with programming (C++, SystemC-TLM), scripting (Python).
Experience with power concepts, trade-offs and low power design principles.
Experience with performance profilers and power measurement tools.
Familiarity with Instruction Set Simulators (ISS), optimized assembly-level kernels (e.g., ARM, Tensilica).
Experience with SoC Architecture, NoCs, memory subsystems, and heterogeneous compute principles.
Experience creating and optimizing machine learning workloads.
Description（岗位职责）
Lead power and performance modeling of IP components and use cases for SoC chips.
Extract system-usage behavior of workloads and design micro-benchmarks.
Lead thermal measurement, performance bottleneck analysis and power characterization.
Perform modeling at the right level of abstraction given model purpose.
Partner across disciplines to problem solve, build new methodologies and coordinate multiple initiatives.
Ability to operate in a cross-functional environment.
Additional Requirements（额外要求）
Bachelors degree in EE, CS or equivalent experience.
3+ years of experience with C++ programming.
2+ years of experience with SystemC/TLM2 programming.
Experience with CV/ML algorithms.
Computer architecture experience, including CPU and domain-specific/ML accelerators.
Familiarity with power management principles, thermal and di/dt analysis, multi-voltage designs, DVFS and UPF concepts.
Experience with thermally constrained power/performance optimization on embedded devices.
Experience with bare-metal programming, micro-benchmarking, etc.
Experience with gathering and interpreting performance counters using tools like perf, VTune, etc.
Experience in building performance models for custom accelerator and SOC pipelines.
