Meta AR/VR Job | Display System Architect
Job（岗位）: Display System Architect
Type（岗位类型）: Engineering
Citys（岗位城市）: Redmond, WA
Date（发布日期）: 2024-3-18
Summary（岗位介绍）
Meta is the world leader in the design of virtual and augmented reality systems. Come work alongside expert engineers and research scientists to create the technology that makes AR pervasive and universal. Join the adventure of a lifetime as we make science fiction real and change the world.
The APIX Architecture team is seeking a Display Architect to lead the implementation of Meta’s proprietary display IP for AR displays. As a member of the APIX team, the successful candidate will be working closely with other Display architects, Perception and Image Quality team, silicon vendors to design, evaluate performance, and embed Meta’s proprietary IP within the vendor's silicon for future AR products. This role requires close collaboration with multiple teams within the Meta Reality Labs.
The ideal candidate is familiar with display algorithms such as sub-pixel rendering, foveation, dithering, persistence, uniformity compensation, dead pixel compensation algorithms, is comfortable with programming languages such as Python or C++, and has ASIC design background including RTL design, synthesis, and timing, sizing, power and project management analysis. Deep understanding of the display pipeline is required.
Qualifications（岗位要求）
Bachelors degree in Electrical Engineer or Computer Engineering or relevant industry experience
10+ years of experience in research, advanced optics development, or equivalent experience
5+ years of technical leadership experience working with multiple internal and external teams
Understanding of the front-end digital design flow: RTL design, logic synthesis, timing verification
Understanding of pixel pipeline for Displays & Backplane Architectures
Effective communication skills and record of publications
Description（岗位职责）
Lead architecture and development of proprietary display IP for AR displays. Collaborate with display algorithm experts to develop software (Python/C++) models of the algorithms.
Collaborate with Perception and Image quality teams to evaluate performance.
Collaborate with hardware prototyping teams to create hardware evaluation and platforms.
Collaborate with vendors to define high-level IP architecture consistent with vendors technologies and design.
Design and implement the algorithm in Verilog with optimized gate-count, meeting performance targets.
Create gate-level, timing-validated IP for transfer to vendors.
Collaborate with vendors to embed IP within the vendor’s silicon solutions.
Supervise and plan time lines and estimates for executive decisions.
Participate in silicon design reviews with vendors and assess overall digital design flow including verification coverage, clock synthesis, timing signoff.
Collaborate with the system team to bring up and test the algorithm for production readiness.
Additional Requirements（额外要求）
15+ years of experience in research, advanced optics development, or equivalent experience
Ph.D. degree in Electrical Engineering or related field
Prior experience with architecture and design of display IP such as sub-pixel rendering, foveation, dithering, deadpixel, uniformitity, burn-in compensation algorithms
Familiar with compression IP design and power estimation
