Meta AR/VR Job | Design Verification Engineer
Job（岗位）: Design Verification Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2024-4-9
Summary（岗位介绍）
Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta’s Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, through algorithms to architecture, transistors to firmware.
As a Design Verification Engineer at Meta’s Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art graphics, vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art graphics IPs.
Qualifications（岗位要求）
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Track record of 'first-pass success' in ASIC development cycles.
Description（岗位职责）
Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Computer Vision IP’s optimized for XR products and use-cases, defining verification methodologies for each of the different core IPs.
Define, track, and lead the execution of detailed test plans for the different modules and top levels.
Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Support hand-off and integration of blocks into larger SOC environments.
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Additional Requirements（额外要求）
Masters in Electrical Engineering or Computer Science.
Experience in development of UVM based verification environments from scratch.
Experience with Design verification of AR/VR applications like Computer Vision/Graphics/Display.
Experience with revision control systems like Mercurial(Hg), Git.
Experience with low power design.
FPGA implementation and debug experience.
Experience in verification of numerical compute based designs.
