Meta AR/VR Job | ASIC Engineer, Formal Verification
Job（岗位）: ASIC Engineer, Formal Verification
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA
Date（发布日期）: 2023-5-27
Summary（岗位介绍）
Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Qualifications（岗位要求）
Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
5+ years of experience in Formal Verification
Proven understanding of formal verification methodologies, complexity reduction techniques and abstraction techniques
Proven analytical skills to craft novel and creative solutions to tackle industry-level complex designs
Proven communication skills to ensure effective collaboration with cross functional teams
Fluency in hardware description languages, such as SystemVerilog and SVA
Proficiency in scripting languages such as Python, Perl, or Tcl
Experience with JasperGold or VC-Formal
Description（岗位职责）
Provide technical leadership in Formal Verification
Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
Work with Architecture and Design team to come up with Formal driven specification and implementation
Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
Build reusable/scalable environments for Formal Verification and deploying the tools
Evaluate and recommend EDA solutions for Formal Verification
Provide training for internal teams and mentoring engineers related to Formal Verification Technology
Additional Requirements（额外要求）
Experience to quickly understand and interpret specifications and extract design behaviors/properties
Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators
Experience with complex SoCs
Formal verification expertise in clock domain crossing, IP-XACT based register verification and low power
Experience with development of fully automated flows from specification to fully verified designs
Experience with simulators and waveform debugging tools
