Meta AR/VR Job | Research Scientist Intern, Display Backplane & CMOS Imaging Design (PhD)
Type（岗位类型）: Hardware | Research
Citys（岗位城市）: Redmond, WA
Meta Reality Labs brings together a world-class team of researchers, developers, and engineers to create the future of virtual and augmented reality, which will become as universal and essential as smartphones and personal computers are today. And just as personal computers have done over the past 45 years, AR and VR will ultimately change everything about how we work, play, and connect. We are developing all the technologies needed to enable breakthrough AR glasses and VR headsets, including optics and displays, computer vision, audio, graphics, brain-computer interface, haptic interaction, eye/hand/face/body tracking, perception science, and true telepresence. Some of those will advance much faster than others, but they all need to happen to enable AR and VR that are so compelling that they become an integral part of our lives.
Our internships are twelve (12) to sixteen (16) or twenty-four (24) weeks long, and we have various start dates throughout the year.
Currently has, or is in the process of obtaining, a PhD degree in the field of Optical Science or Engineering, Electrical Engineering, Physics, Computational Imaging or a related field.
2+ years experience in CMOS analog or mixed-signal IC circuit design
3+ years experience in mastering CMOS design simulation tools such as Cadence Virtuoso and layout
2+ years experience in CMOS imaging sensor circuit design
Experience in design, layout, and taping out CMOS chips at the standard semiconductor foundry
Interpersonal experience: cross-group and cross-culture collaboration
Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
Develop architecture of display backplane with integration of IR LEDs and imaging sensor, emphasizing circuit design and layout exploration to prove new concepts.
Perform detailed simulation of the circuit function as well as performance
Conduct the detailed layout excise to refine the circuit design and system retrofit
Perform performance analysis on different approaches/designs for key figures of merit.
Collaborate with a larger Meta RLR team to evaluate performance at a system level.
Proven track record of achieving significant results as demonstrated by grants, fellowships, patents, or first-authored publications at leading workshops or conferences such as IEEE, SID, JSID etc.
Demonstrated experience via an internship, work experience, or project-based coursework.
Multiple CMOS tape-out experiences using advanced CMOS nodes such as 14nm or below.
Intent to return to a degree-program after the completion of the internship/co-op.