Meta AR/VR Job | Digital Modeling Engineer
Job（岗位）: Digital Modeling Engineer
Citys（岗位城市）: Sunnyvale, CA | Redmond, WA | Austin, TX
We are looking for a Digital Modeling Engineer to contribute to architectural advancements to our framework for capturing a single source of truth for our designs, and collaborate with our world-class group of researchers and engineers to develop and deploy this technology. We apply this framework at the block, subsystem and SoC levels to automate the generation of consistent design, modeling, verification, synthesis and firmware views of our optimized mixed reality IP. The ideal candidate will understand the full spectrum of design and verification choices when tackling integration aspects of heterogeneous SoCs. Beyond coding, the candidate will contribute to the specification, deployment and the evangelization of generator methodologies across the team.
Successful candidates for this role will also have a good grasp on SoC architecture of heterogeneous processing subsystems, experience abstracting and automating design and modeling/verification tasks, background collaborating in a cross-functional environment, and a hands-on approach to problem-solving.
BS/MS CS or equivalent experience
3+ years of experience integrating SoCs or complex IP-based subsystems as a Silicon Architect, Digital Design Engineer, or NoC Architect, or equivalent
Experience with programming languages (C/C++ and Python or similar), script automation and data visualization
Experience in employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary design issues
Extensive experience automating design-oriented tasks
Maintain and extend the generator framework.
Evangelization of generator methodology across all HW/SW teams.
Hands-on development to enable HW architecture, micro-architecture, design, physical implementation, prototyping, performance analysis/optimization, and testing for multiple projects.
Work cross-functionally with SoC architecture, Modeling, FW, prototyping and development teams.
Work effectively as an individual and in a multidisciplinary international team.
Hands-on development experience in System Verilog and UVM
Experience with performance modeling In SystemC/TLM2 or equivalent
Experience collaborating and/or leading in a team environment