Meta AR/VR Job | ASIC Graphics Engineer
Job（岗位）: ASIC Graphics Engineer
Citys（岗位城市）: Remote, Poland | Remote, Sweden | Remote, Ireland | Remote, Spain | Remote, UK | London, UK
Reality Labs focuses on delivering Meta’s vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. The Meta Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, audio, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
We are growing our ASIC Architecture, Design and Verification teams within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using their skills to implement and contribute to the development and optimization of power efficient graphics IPs.
Bachelor’s in Electrical Engineering/Computer Science or equivalent experience.
3+ years of experience as a Digital Design Engineer, Design Verification Engineer or Graphics Architect.
Knowledge of digital ASICs design/verification flows.
Experience in digital design µArchitecture and RTL coding/synthesis, or SystemVerilog OVM/UVM design verification.
Experience with at least 1 procedural programming language (C, C++, Python etc.).
Experience working in a fast moving, cross-functional environment.
Contribute to scalable architecture and µArchitecture designs for low-power graphics IPs.
Contribute to the top-level µArchitecture definition and necessary RTL development.
Define verification methodologies for each of the different core IP.
Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
Drive the chip-level integration, verification plan development and verification.
Support the test program development, chip validation and chip life until production maturity.
Work with FPGA/emulation engineers to perform early prototyping.
Support hand-off and integration of blocks into larger SOC environments.
Assist with performance/power analysis of IP models.
Work with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading graphics IP’s optimized for XR products and use-cases.
MS in EE/CS or equivalent
Experience with Machine learning, graphics or computer vision accelerators.
Experience with low power design and optimization.
Experience with system architecture and rendering software stack.