Meta AR/VR Job | Digital Design Engineer
Job（岗位）: Digital Design Engineer
Citys（岗位城市）: Remote, US | Sunnyvale, CA | Redmond, WA
Reality Labs focuses on delivering Meta’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Meta Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, firmware, and algorithms.
We are growing our ASIC Design and µArchitecture team within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using their digital design skills to implement and contribute to the development and optimization of power efficient graphics IPs.
3+ years of experience as a Digital Design Engineer and/or a Chip Lead.
Experience in RTL coding, synthesis and/or SoC Integration.
Experience in digital design µArchitecture.
Experience with at least 1 procedural programming language (C, C++, Python etc.).
Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Contribute to scalable architecture and µArchitecture designs for low-power graphics IP design.
Drive the top-level µArchitecture definition and develop the necessary RTL.
Drive the chip-level integration, verification plan development and verification.
Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
Contribute to ASIC digital µArchitecture, design and verification.
Support the test program development, chip validation and chip life until production maturity.
Work with FPGA engineers to perform early prototyping.
Support hand-off and integration of blocks into larger SOC environments.
Assist with performance/power analysis of IP models.
Experience with Machine learning, graphics or computer vision accelerators.
SystemVerilog OVM/UVM experience.
Experience in SoC integration and ASIC architecture.
Experience with low power design and optimization.
Experience with design synthesis and timing optimization.
Master’s degree in Electrical Engineering/Computer Science.