Microsoft AR/VR Job | Senior Design Verification Engineer (CPU/L2)

Job(岗位): Senior Design Verification Engineer (CPU/L2)

Type(岗位类型): Hardware Engineering

Citys(岗位城市): Raleigh, United States | Austin, United States

Date(发布日期): 2021-9-21


The silicon computing development team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from traditional computing solutions to artificial intelligence and augmented reality. We are responsible for delivering cutting-edge, custom CPU and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.


  • Candidate must have at least a bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related degree
  • 5+ years of experience in design verification with a proven track record of delivering complex high-quality CPU’s and/or cache designs
  • 3+ years of experience working on complex CPU architectures and general computer architectures.

Preferred Qualifications:

  • Deep working knowledge of various CPU related architectural and micro-architectural concepts including data caches, memory coherence, virtualization, address translation, load & store operations, atomic instructions, data fault, memory management concepts and/or working knowledge of integer and floating-point operations, pipeline hazards, out-of-order execution, general purpose registers, instruction completion, write-back concepts, trace, performance profiling, and hardware debug functions.
  • In depth knowledge of verification principles, test benches, assembly languages, stimulus generation, UVM/OVM, SystemVerilog and coverage
  • Extensive experience debugging designs as well as creating and using various simulation environments
  • Scripting language such as Python or Perl
  • Have successfully developed and driven verification technical strategy and capabilities in a particular area
  • Proficient leadership skills
  • Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
  • Experience building and optimizing simulation, emulation, and/or FPGA verification environments, tools, flows, and methodologies
  • Experience with Agile software practices

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.




In this role, you will:

  • Establish yourself as an integral member of a pre-silicon verification team for the development of custom CPU and L2 components with focus on micro-architectural based functions and features
  • Work with a team to write, execute, enhance, and debug constrained random stimulus
  • Develop UVM components to interface between test code and verification simulation environments
  • Collaborate across verification teams on vertical and horizontal reuse of components
  • Define and implement functional coverage and drive coverage closure
  • Triage and debug testbench, simulation, and emulation fails