Meta AR/VR Job | Reality Labs ASIC Engineering Manager, Design Verification
Job（岗位）: Reality Labs ASIC Engineering Manager, Design Verification
Type（岗位类型）: Hardware
Citys（岗位城市）: Remote, US | Sunnyvale, CA | Redmond, WA | Austin, TX
Date（发布日期）: 2022-9-21
Summary（岗位介绍）
The ideal candidate will be a consensus driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.
Qualifications（岗位要求）
B.S/M.S/Ph.D. degree in Computer Engineering or Electrical Engineering
5+ years technical leadership experience managing digital design/verification teams
Track record of first-pass success in ASIC Development
Experience working across multiple projects and adjusting priorities in partnership with stakeholders
Experience managing and delivering SV/UVM constrained random test benches
Experience with interpreting functional specs and creating comprehensive test plan
Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium simulator, Verdi, JasperGold or VC Formal
Description（岗位职责）
Manage an ASIC design verification team responsible for various pervasive IPs in an SOC
Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure
Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams
Collaborate with IP development teams for integration of pervasive IPs into their design
Partner with SoC and IP architects to drive roadmaps for future designs
Support organization wide initiatives on improving design and verification methodologies
Define, implement and maintain key performance indicators (KPI) for areas of responsibility
Partner with technical program management to communicate status, issues and project updates
Identify candidates, hire, support and train a team of ASIC engineers in order to develop products on time
Additional Requirements（额外要求）
Chip-level architecture, µArchitecture, design and design verification experience
Experience designing of on-chip power controllers
Deep understanding of on-chip interface protocols (ARM AMBA, OCP)
Capable of dealing with ambiguity in a fast changing consumer electronics field
Results oriented, self-motivated, proactive with demonstrated creative & critical thinking skills
Skilled in design and verification using SystemVerilog/UVM and automation languages such as Python
