Meta AR/VR Job | Silicon DFT Manager, Reality Labs

Job(岗位): Silicon DFT Manager, Reality Labs

Type(岗位类型): Engineering

Citys(岗位城市): Sunnyvale, CA | Redmond, WA | Austin, TX

Date(发布日期): 2022-4-6


Meta’s Reality Labs (RL) focuses on connecting people through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of these products require custom silicon. The Silicon Team is driving the state-of-the-art forward with breakthroughs in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.

As a DFT Manager in the Silicon organization, you will actively drive DFT solutions for our custom silicon roadmap. Through this highly visible role, you will be managing the team effort and interfacing with multiple disciplines, with a critical impact on getting functional high-quality products to millions of customers.


3+ years of technical leadership experience

Design for Test experience on complex SoC’s including architecture specification, Implementation, test pattern development and verification

Master’s degree in Engineering with 6+ years of experience or BS and 8+ years Industry experience

Knowledge about industry standards and practices in DFT, ATPG, JTAG, Memory BIST, and trade-offs between test quality and product impact (power, performance, area, schedule)

Experience with yield enhancement methods such as memory repair and in-system operation

Proficient with commercially available DFT, design and verification EDA tools


Inspire and lead a team of DFT Methodology and CAD engineers

Work with the Silicon teams to establish DFT requirements and the DFT Architecture needed to achieve product quality goals

Develop and implement DFT features and methodologies optimized for PPA and verified

Improve execution efficiency and QOR through flow automation and dashboard checks

Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts

Support silicon bring-up, debug and ramp to production

Work closely with industry partners including EDA, IP and ASIC vendors on tools, flows and methodology

Additional Requirements(额外要求)

Results oriented, self-motivated, proactive with demonstrated creative & critical thinking skills

Skilled in automation languages such as Python, and proven CAD software engineering skills

Experience in debugging DFT patterns in simulation and on ATE

Experience with running synthesis, developing timing constraints for DFT modes, and analysis of SDF timing back-annotated simulations

Experience with power-aware DFT, power delivery networks and their unique interaction with DFT architectures and implementations

Experience with Analog DFT and Analog Mixed Signal IP test methods and integration

Capable of dealing with ambiguity in a fast changing consumer electronics field, with experience leading through periods of rapid growth