Meta AR/VR Job | ASIC Engineer, Reality Labs (University Grad)
Job（岗位）: ASIC Engineer, Reality Labs (University Grad)
Type（岗位类型）: Design | Engineering, Hardware
Citys（岗位城市）: Sunnyvale, CA
Reality Labs brings together a world-class team of researchers, developers, and engineers to create the future of virtual and augmented reality, which together will become as universal and essential as smartphones and personal computers are today. And just as personal computers have done over the past 45 years, AR and VR will ultimately change everything about how we work, play, and connect.
We are developing all the technologies needed to enable breakthrough AR glasses and VR headsets, including optics and displays, computer vision, audio, graphics, brain-computer interface, haptic interaction, eye/hand/face/body tracking, perception science, and true telepresence. Some of those will advance much faster than others, but they all need to happen to enable AR and VR that are so compelling that they become an integral part of our lives.
As an ASIC Engineer, you will work with a world-class group of researchers and engineers and use your digital design and/or verification skills to contribute to development and optimization of algorithms in hardware. You could also be involved in the design and implementation of the testing infrastructure to verify these new core IP designs.
Currently has, or is in the process of obtaining, a Bachelors or Masters degree in Electrical Engineering, Computer Science or related technical field. Degree must be completed prior to joining Meta.
Experience in digital design using Verilog, SystemVerilog or VHDL
Experience with Python, Perl, TCL or equivalent shell scripting language
Experience in Digital Design Verification (DV)
C/C++ coding, debugging experience
Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
Work with architects and logic designers to understand the µArchitecture of digital designs
Work with architects and logic designers defining and implementing verification methodologies
Define and track detailed test plans for the different modules and top levels
Implement scalable test benches including checkers, reference models, and coverage groups
Keep track of coverage metrics and bugs encountered and fixed
Implement self-checking directed and random tests
Develop the scripts and code necessary for proper automation
Support activities related to integration of block-level testbenches into top level design
Experience in digital ASIC architecture and µArchitecture.
Experience in ASIC/FPGA design methodologies.
Experience working and communicating cross-functionally in a team environment.