Meta AR/VR Job | Silicon System Validation Engineer
Job（岗位）: Silicon System Validation Engineer
Type（岗位类型）: Engineering | Hardware
Citys（岗位城市）: Sunnyvale, CA | Redmond, WA | Austin, TX
The Meta Reality Labs team is building products that make it easier for people to connect with the ones they love most. We are a team of world-class experts developing and shipping products at the intersection of silicon, hardware, software, and content. As a Silicon System Validation Engineer, you will be part of the Vision/Machine Learning IP team validating our Vision/ML algorithms on high performance and low power silicon for our Augmented Reality Glasses.
Bachelor’s degree in Computer Engineering or Electrical Engineering
5+ years of hands-on experience in silicon validation of complex IPs
Experience in leading silicon validation planning, execution, development, and validation signoff
Experience influencing design, DV, Post-Silicon validation teams to optimize the usage of Pre-Silicon Prototype platforms
SystemVerilog Testbenches, Bus Functional Models, and Transactors
Familiarity with Python and C++ Object Orienting Programming
Problem solving, debug, and whiteboard skills
Experience working in a cross functional and cross site team environment
Effective communication and prioritization skills
IP and SoC system validation plan development, execution and sign-off.
Identify and communicate technical risks related to the project to the stakeholders.
Plan, organize, and oversee pre-silicon validation on emulation platforms such as Synopsys HAPS and Zebu and silicon bring-up across multiple System-On-Chips (SoC).
Understands system Hardware/Software/Firmware components as a whole, drive test execution and debug with cross functional teams.
Lead lab debug, silicon bug reproduction, failure analysis, and failure report activities.
Work with cross-functional teams (i.e. architecture, IP, Firmware, SoC, and product engineer teams) to generate validation reports for SoC and systems.
Work in an agile environment, changing roadmaps and be able to adapt validation plans based on algorithm and silicon changes.
Master’s degree in Computer Engineering or Electrical Engineering
Knowledge of ASIC design flow, silicon foundry test flow, and silicon firmware development process
Experience in building silicon validation infrastructure and test automation
Experience and knowledge of bus protocols such as AXI, AHB, APB, OCP