Meta AR/VR Job | Silicon Physical Design Engineer Intern, ASIC Methodology

Job(岗位): Silicon Physical Design Engineer Intern, ASIC Methodology

Type(岗位类型): Engineering | Hardware

Citys(岗位城市): Sunnyvale, CA

Date(发布日期): 2022-1-17

Summary(岗位介绍)

Reality Labs (RL) focuses on delivering Meta’s vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware and algorithms.

We are seeking an intern to help develop ASIC physical design methodologies from RTL2GDS for enabling custom Silicon for Meta’s future products.

Our internships are twelve (12) to sixteen (16) weeks long and we have various start dates throughout the year.

Qualifications(岗位要求)

Currently has, or is in the process of obtaining, a Master’s degree in Electrical Engineering, or Computer Science with a focus on VLSI, or a related field

Conversant in at least one scripting language like Python, Ruby, Tcl or equivalent

Understanding of physical design concepts like synthesis, place and route, static timing analysis, power estimation

Knowledge of circuit design and device physics fundamentals

Interpersonal experience: cross-group and cross-culture collaboration

Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment

Description(岗位职责)

Develop RTL2GDS ASIC design CAD flows for physical design implementation

Benchmark novel physical design methodologies, new process technologies, and recipes for Power Performance Area (PPA) improvement

Deliver physical design for low-power designs on advanced technology nodes

Evaluate and onboard new Electronic Design Automation (EDA) tools to enable robust ASIC methodologies

Additional Requirements(额外要求)

Experience with one or more physical design EDA tools like Design Compiler, IC Compiler II, Innovus, Primetime/Tempus, Formality/Conformal

Understanding of the physical design constraints, timing, floorplan, upf, required to drive standard EDA tools

Intent to return to degree-program after the completion of the internship

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