Meta AR/VR Job | Design Verification Engineer Intern, Computer Vision Accelerators
Type（岗位类型）: 3D Product Design | Engineering, Hardware
Citys（岗位城市）: Sunnyvale, CA
Reality Labs (formerly Facebook Reality Labs) focuses on delivering Meta’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Silicon Team is driving the state of the art forward with breakthrough work in computer vision, ISP, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
As a Design Verification Intern at Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verification skills to implement the testing infrastructure to validate new core IP implementations and contribute to the development and optimization of state of the art computer vision accelerators. You will work closely with architects and designers in creating test bench requirements, infrastructure and test cases for state of the art computer vision IPs.
Our internships are twelve (12) to sixteen (16) weeks long and we have various start dates throughout the year.
Currently has, or is in the process of obtaining, a Bachelor’s degree in Electrical Engineering or Computer Science or a related field
Knowledge of digital ASICs design flows
Experience with at least 1 procedural programming language (C, C++, etc)
Experience with Python, or similar, language
Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
Interpersonal experience: cross-group and cross-culture collaboration
Work with design and verification engineers in defining verification methodology improvements using SystemVerilog
Improve build flow , regression flow and automatization flow using scripts in python
Currently has, or is in the process of obtaining, a Master’s degree in Electrical Engineering or Computer Science, or a related field
Intent to return to degree-program after the completion of the internship
Knowledge of computer architecture
C, C++ coding, debugging experience
Experience in digital design projects
System Verilog & UVM coding experienc2