Meta AR/VR Job | Design Verification Engineer
Job（岗位）: Design Verification Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Tel Aviv, Israel
Date（发布日期）: Before 2021-12-14
Summary（岗位介绍）
Facebook Reality Labs focuses on delivering Facebook’s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, ISP, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
We are growing our ASIC Design and µArchitecture team within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using their digital design skills to implement and contribute to the development and optimization of power efficient Computer Vision and ISP IPs.
As a Design Verification Engineer at Facebook Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.
Qualifications（岗位要求）
2+ years of System Verilog OVM/UVM DV experience.
Knowledge of Python, Perl, shell scripting.
Knowledge with assertions (SVA) or others.
Knowledge of digital ASICs design flows.
Bachelors degree in Electrical Engineering or Computer Science or equivalent experience.
Description（岗位职责）
Work with researchers and architects defining verification methodologies for each of the different core IP.
Define and track detailed test plans for the different modules and top levels.
Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
Keep track of coverage metrics and bugs encountered and fixed.
Implement self-testing directed and random tests.
Support post silicon bringup and debug activities.
Ability to communicate clearly.
Additional Requirements（额外要求）
C, C++ coding, debugging experience.
Experience as a digital design engineer.
Experience with low power design.
FPGA implementation and debug experience.
Self-motivated and team player.
Masters in Electrical Engineering or Computer Science.
