Meta AR/VR Job | Digital Modeling Engineer
Job（岗位）: Digital Modeling Engineer
Type（岗位类型）: Hardware
Citys（岗位城市）: Sunnyvale, CA | Redmond, WA | Austin, TX | Remote, US
Date（发布日期）: Before 2021-12-14
Summary（岗位介绍）
Facebook Reality Labs, focuses on delivering Facebook's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
We are looking for a Digital Modeling Engineer who will work with a world-class group of researchers and engineers. This ideal candidate will assist the engineering team with cycle-accurate or -approximate SystemC models for custom silicon IP blocks, sub-units, and systems aimed at verifying the functional correctness and performance of the design as well as allowing the simulation of realistic traffic.
Qualifications（岗位要求）
Bachelor degree in EE/ECE/CS
7+ years experience in object oriented design and C++ implementation
Knowledge of hardware design and simulation
Experience with SystemC modeling using the TLM2 standard
Experience with debugging and understanding model discrepancies
Experience with communicating and working as an individual and in a multidisciplinary team
Description（岗位职责）
Create model specification documents based on architecture and micro-architecture specifications
Implement transaction level models (TLM) of configurable hardware IP blocks, sub-units and systems, as well as behavioral components
Debug and analyze performance discrepancies between SystemC model and RTL implementation
Create and maintain Makefiles and Python programs supporting SystemC model generation
Perform audits of existing verification plans and verification tests to determine compliance with quality goals
Additional Requirements（额外要求）
Master degree in EE/ECE/CS
Experience in SystemC/TLM2 cycle-accurate modeling
Experience with Makefile creation and Python (or other scripting languages)
Experience with mixing timed and untimed TLM2 models
Experience with cycle-accurate SoC performance model environments
Experience to collaborate and/or lead in a team environment
